3 #include <kiba/containers/array.h>
4 #include <kiba/core/id.h>
5 #include <kiba/core/types.h>
6 #include <kiba/gpu/enums.h>
7 #include <kiba/gpu/internal.h>
8 #include <kiba/gpu/limits.h>
9 #include <vulkan/vulkan.h>
24 enum gpu_texture_format format;
25 enum gpu_present_mode present_mode;
38 usize mip_level_count;
41 enum gpu_texture_dimension dimension;
43 enum gpu_texture_format format;
45 enum gpu_texture_usage usage;
53 identifier tracker_id;
60 enum gpu_texture_use start_use;
61 enum gpu_texture_use cur_use;
74 enum gpu_texture_format format;
75 enum gpu_texture_view_dimension dimension;
76 enum gpu_texture_aspect aspect;
78 usize mip_level_count;
79 usize base_array_layer;
80 usize array_layer_count;
96 enum gpu_buffer_usage usage;
102 identifier tracker_id;
109 enum gpu_buffer_usage start_use;
110 enum gpu_buffer_usage cur_use;
115 enum gpu_texture_format format;
116 enum gpu_texture_use source_use;
117 enum gpu_texture_use target_use;
122 enum gpu_buffer_usage source_usage;
123 enum gpu_buffer_usage target_usage;
146 enum gpu_device_resource_type {
147 GPU_DEVICE_RESOURCE_TEXTURE,
148 GPU_DEVICE_RESOURCE_TEXTURE_VIEW,
149 GPU_DEVICE_RESOURCE_PIPELINE,
150 GPU_DEVICE_RESOURCE_PIPELINE_LAYOUT,
151 GPU_DEVICE_RESOURCE_SHADER_MODULE,
152 GPU_DEVICE_RESOURCE_BUFFER,
153 GPU_DEVICE_RESOURCE_COMMAND_ENCODER,
157 enum gpu_device_resource_type type;
172 usize destruction_queue_index;
184 GPU_STORE_OP_DISCARD,
194 static inline enum gpu_attachment_ops gpu_operations_to_attachment_ops(
struct gpu_operations ops) {
195 enum gpu_attachment_ops ret = 0;
196 if (ops.load == GPU_LOAD_OP_LOAD) {
197 ret |= GPU_ATTACHMENT_OP_LOAD;
199 if (ops.store == GPU_STORE_OP_STORE) {
200 ret |= GPU_ATTACHMENT_OP_STORE;
220 u32 color_attachment_count;
230 enum gpu_shader_type type;
237 enum gpu_shader_type type;
245 GPU_ADDRESS_MODE_CLAMP_TO_EDGE,
246 GPU_ADDRESS_MODE_REPEAT,
247 GPU_ADDRESS_MODE_MIRROR_REPEAT,
248 GPU_ADDRESS_MODE_CLAMP_TO_BORDER,
252 GPU_FILTER_MODE_LINEAR,
253 GPU_FILTER_MODE_NEAREST,
254 } mag_filter, min_filter, mipmap_filter;
256 f32 load_min_clamp, load_max_clamp;
262 array_of(gpu_bind_group_layout) bind_group_layouts;
274 enum gpu_vertex_format format;
279 enum gpu_step_mode step_mode;
285 const char *entry_point;
291 enum gpu_primitive_topology topology;
293 enum gpu_front_face front_face;
294 enum gpu_cull_mode cull_mode;
296 enum gpu_polygon_mode polygon_mode;
306 enum gpu_texture_format format;
308 enum gpu_color_writes write_mask;
314 const char *entry_point;
320 enum gpu_texture_format format;
321 b8 depth_write_enabled;
322 enum gpu_compare_func depth_compare;
326 enum gpu_compare_func compare;
329 GPU_STENCIL_OPERATION_KEEP,
330 GPU_STENCIL_OPERATION_ZERO,
331 GPU_STENCIL_OPERATION_REPLACE,
332 GPU_STENCIL_OPERATION_INVERT,
333 GPU_STENCIL_OPERATION_INCREMENT_CLAMP,
334 GPU_STENCIL_OPERATION_DECREMENT_CLAMP,
335 GPU_STENCIL_OPERATION_INCREMENT_WRAP,
336 GPU_STENCIL_OPERATION_DECREMENT_WRAP,
337 } fail_op, depth_fail_op, pass_op;
340 u8 read_mask, write_mask;
Central allocator structure.